Affiliations: Centre for Development of Advanced Computing, Ministry of Communications and Information Technology, Government of India, Noida, India | Department of Electrical Engineering, Jamia Millia Islamia, Central University, New Delhi, India
Note: [] Corresponding author: Mohammad Ayoub Khan, Centre for Development of Advanced Computing, Ministry of Communications and Information Technology, Government of India, B 30, Sector 62, Institutional Area, Noida, UP 201 307, India. E-mail: [email protected].
Abstract: The conventional two-dimensional (2-D) integrated circuit (IC) has limited scope for floor planning and therefore limits the performance improvements resulting from the Network-on-Chip (NoC) paradigm. The arrangement of 3-D also offers opportunities for new circuit architecture based on the geometric capacity that provide greater numbers of interconnections among multi-layer active circuits. The emerging 3-D VLSI Integration and process technologies allow the new design opportunities in 3-D NoC. The 3-D NoC can reduce significant amount of wire length for local and global interconnects. The role of bus and arbitration logic is equally important in the design of NoC. The performance of the traditional bus is degraded by the increasing number of processing elements and transaction oriented model [On-Chip Communication Architectures, Morgan Kaufmann, 2008]. This has attracted much attention for applying wireless network protocols as CDMA, TDMA, dTDMA, etc. in SoC. The TDMA systems use a fixed number of timeslot. This protocol wastes bandwidth when some timeslots are allocated but not used. The dynamic TDMA (dTDMA) bus arbiter dynamically grows and shrinks the number of timeslots to match the number of active transmitters [in: VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design, 19th International Conference on, January 2006, p. 8]. In this paper, we present a design of high-speed switch and layer arbiter for inter-layer communications in 3-D Network-on-Chip. We have developed a Register Transfer Logic (RTL) level simulation model to evaluate the performance of proposed arbiter. A 640-bit message with uniform random destination data pattern was injected per IP per machine clock cycle. The worst case latency for the proposed design is 35 clock cycles. The presented architecture demonstrates their superior functionality in terms of speed and latency compared with existing implementation. The design is synthesized using 0.18 micron TSMC Technology [Taiwan Semiconductor Manufacturing Company, Ltd, 2011].
