Affiliations: IBM High Performance Computing and Communications, 472 Wheelers Farms Rd. MS93, Milford, CT 06460-1844, USA, [email protected], +1 203 783 4380 | Computer & Communications Research Center and Department of Computer Science, Bryan 405, Box 1115, Washington University, One Brookings Drive, St. Louis, MO 63130-4899, USA, [email protected], +1 314 935 4621
Note: [] This work is supported in part by Bellcore, BNR, DEC, Italtel SIT, NEC, NTT, SW Bell, Synoptics, and NSF grant DCI-8600947 (research done while at Washington University).
Abstract: We have proposed a new architecture called Axon that meets the challenges of delivering high network bandwidth directly to applications. Its novel aspects include: an integrated design of host and network interface hardware, operating systems, and communication protocols; the proper division of hardware and software function; reorganisation of end-to-end protocols to take advantage of the increased functionality of the emerging high speed internetworks; and a pipelined interface between the network and host memory with no packet buffering. The pipelined network interface performs critical per packet processing in hardware as packets flow through the pipeline, without imposing any store-and-forward buffering of packets. This requires the design of error and flow control mechanisms to be simple enough for implementation in the network interface hardware, while providing the functionality required by applications. This paper describes the design of the host-network interface, and, in particular, the hardware design of the critical per packet processing with emphasis on error and flow control. An extensive simulation model of the network interface hardware has been used to determine the feasibility and performance of hardware implementation of these functions.
Keywords: Gigabit Network Interface, High Speed Protocols, Distributed Virtual Memory
