Affiliations: Department of Electrical and Computer Engineering, and Center for Communications and Signal Processing, North Carolina State University, Raleigh, N.C. 27695-7914 | Department of Computer Science, and Center for Communications and Signal Processing, North Carolina State University, Raleigh, N.C. 27695-8206 | V57/B660, IBM, P.O. Box 12195, Research Triangle Park, N.C. 27709
Note: [] Supported in part by DARPA under grant no. DAEA18-90-c-0039.
Abstract: We consider a synchronized bufferless Clos ATM switch with input cell processor queues. The arrival process to each input port of the switch is assumed to be bursty and it is modelled by an Interrupted Bernoulli Process. Two classes of cells are considered. Service in an input cell processor queue is head-of-line without preemption. In addition, push-out is used. That is, a high priority cell arriving to a full queue takes the space occupied by the low priority cell that arrived last, as long as the cell is not in service. Each cell processor queue is modeled as a priority IBP/Geo/1/ K + 1 queue with push-out. We first present an exact analysis of this priority queue. The results obtained are then used in an approximation algorithm for the analysis of the ATM switch. Validation tests using simulation data shows that the approximation algorithm has a good accuracy.
