A Scheduling Strategy for Synchronous Elastic Designs

Issue title: Application of Concurrency to System Design, the Eighth Special Issue

Article type: Research Article

Authors: Carmona, Josep | Júlvez, Jorge | Cortadella, Jordi | Kishinevsky, Michael

Affiliations: Universitat Politècnica de Catalunya, Barcelona, Spain. [email protected] | Universidad de Zaragoza, Zaragoza, Spain. [email protected] | Universitat Politècnica de Catalunya, Barcelona, Spain. [email protected] | Intel Corporation, Hillsboro, USA. [email protected]

Note: [] Address for correspondence: Universitat Politècnica de Catalunya, Carrer de Jordi Girona, Barcelona, Spain

Abstract: With the scaling of process technologies, communication delays represent a bottleneck for the performance of circuits. One of the main issues that has to be handled is the variability of such delays. Latency-insensitive circuits offer a form of elasticity that tolerates variations in those delays. This flexibility usually requires the addition of a control layer that synchronizes the flow of information. This paper proposes a method for eliminating the complexity of the control layer, replacing it by a set of iterative schedulers that decide when to activate computations. Unlike previous approaches, this can be achieved with low complexity algorithms and without extra circuitry.

DOI: 10.3233/FI-2011-411

Journal: Fundamenta Informaticae, vol. 108, no. 1-2, pp. 1-21, 2011