Application of Concurrency in the Asynchronous Design of Write-after-read Operations

Issue title: Application of Concurrency to System Design

Article type: Research Article

Authors: Toosizadeh, Navid | Zaky, Safwat G.

Affiliations: Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada, 10 King's College Road, Toronto, Ontario, M5S 3G4. E-mail: [email protected]; [email protected]

Abstract: This paper introduces enhancements to the synthesis of circuits that involve write-afterread (WAR) operations and use the four-phase handshake protocol. The paper demonstrates that the use of edge-triggering makes possible many useful trade-offs among speed, area and powerdelay product. Significant increases in speed are possible as a result of increased concurrency in the circuit's operation, which compensates for much of the penalty associated with the down phase of the four-phase protocol. It is also shown that concurrency can be increased by the judicious insertion of T-elements in the system's control structure. Simulation results for a 16-bit accumulator showed a speed increase of 50% and a reduction of 23% in the power-delay product. The speed of a radix-4 Booth multiplier increased by over 27% and its area and energy consumption were reduced by 5%. These results were derived using test circuits synthesized by Balsa and implemented in Synopsys using 180-nm technology.

Keywords: Write-after-read operation, Asynchronous circuits, Syntax-directed compilation, Sequencer, S-element, T-element, Handshake circuits, Handshake components, Concurrency

DOI: 10.3233/FI-2009-141

Journal: Fundamenta Informaticae, vol. 95, no. 1, pp. 31-52, 2009