Affiliations: [a] Bialystok University of Technology, Bialystok, Poland. [email protected]
| [b] Gymnasium, Darmstadt, Germany. [email protected]
| [c] Belarusian State University of Informatics and Radioelectronics, Minsk, Belarus. [email protected]
Correspondence:
[†]
Address for correspondence: Bialystok University of Technology, Bialystok, Poland.
Note: [*] This work was supported by the grant WZ/WI-IIT/2/2020 from Bialystok University of Technology, Faculty of Computer Science
Abstract: This paper presents the universal address sequence generator (UASG) for memory built-in-self-test. The studies are based on the proposed universal method for generating address sequences with the desired properties for multirun march memory tests. As a mathematical model, a modification of the recursive relation for quasi-random sequence generation is used. For this model, a structural diagram of the hardware implementation is given, of which the basis is a storage device for storing so-called direction numbers of the generation matrix. The form of the generation matrix determines the basic properties of the generated address sequences. The proposed UASG generates a wide spectrum of different address sequences, including the standard ones, such as linear, address complement, gray code, worst-case gate delay, 2i, next address, and pseudorandom. Examples of the use of the proposed methods are considered. The result of the practical implementation of the UASG is presented, and the main characteristics are evaluated.
Keywords: antirandom tests, controlled random tests, multiple tests, RAM testing
