Implementation of integrated circuit and design of SAR ADC for fully implantable hearing aids

2.1Considerations for design of ADC for fully implantable hearing aids

The audible range of humans is a frequency range of 20–20,000 Hz, as shown in Fig. 1 [6, 7]. The area of interest of ADC design is a speech range with a frequency range of 100–8,000 Hz. The characteristics for each frequency band are shown in Table 1, and 500–4,000 Hz with speech intelligibility of 83% in the speech area is important [8]. Therefore, a sampling frequency of 32 kHz for speech signal processing based on the Nyquist theory is selected. In order to determine the resolution of the ADC, in accordance with the distinguishable quality of the minimum sound pressure level in the speech area, we considered the operating characteristics and dynamic range of an implantable microphone. The implantable microphone operating characteristics are shown in Fig. 2. The microphone output signal was amplified to 25 dB to meet the input voltage range of the designed ADC. Because the 25 dB amplified 50 mV ac peak signal became an 889 mV ac peak signal, to avoid half wave clipping, the ADC needed an input bias voltage of 900 mV, which is the closest voltage to 889 mV. For the 1.8 v driven ADC, the LSB resolution of the 16 bit ADC is 27.46 μV, and the minimum sound pressure level of the speech area in Fig. 1 is about 45 dB SPL, whose voltage level is equivalent to 622 μV. Therefore, the 16 bit ADC can provide a sufficient resolution to be discriminated even in the 40 dB region. The resolution of the ADC was selected as 16 bit.

Figure 1.

Graph of audible range.

Figure 2.

Operating characteristics of implantable microphone.

Figure 3.

Minimum sound pressure level of each bit to distinguish speech regions.

The speech and audio application fields generally require a high resolution and slow conversion speed. Therefore, the design target of ADC for fully implantable hearing aids was determined to be 16 bit and 32 kHz. The structure of a typical ADC in accordance with the resolution and conversion speed is shown in Fig. 3, and the ADC structure of advantages and disadvantages according to Fig. 3 is shown in Table 2 [9]. As shown in Fig. 3 and Table 2, the SAR ADC and Δ-Σ ADC conform to the design target. Because of the characteristic of fully implantable hearing aids of being permanently implanted in the body, the ADC of fully implantable hearing aids was selected as an SAR ADC with advantages of power consumption and size.

2.2Design of SAR ADC

The designed SAR ADC consists of sample and hold, a voltage follower, comparator, and R-2R ladder DAC, as shown in Fig. 4. Therefore, the SAR ADC design focused on low power consumption and a small size.

Figure 4.

Entire circuit diagram of (a) sample and hold, (b) comparator, (c) R-2R ladder DAC, (d) designed SAR ADC.

The designed sample and hold circuit consists of switches, a sampling capacitor, inverter, and voltage follower. If the switch works in the on/off positions, the charge injection and clock feedthrough will be produced by a parasitic capacitor. This problem affects the linearity due to the leakage current. In order to solve the problem of non-linearity, there are ways to reduce the size of the switch and increase the value of the sampling capacitor. However, increasing the value of the sampling capacitor also increases the size and power consumption. In order to reduce the leakage current, the switch size is minimized. In addition, the charge injection is an element that disturbs linearity. In order to prevent the charge injection, a CMOS switch and dummy switch have been used. Because the electric charges of the NMOS and PMOS have opposite polarity, the charge injection is reduced. The non-linearity problem is compensated for by the preceding method, but not completely resolved. Therefore, bit conversion is performed before the occurrence of LSB error due to the non-linearity problem, as shown in Fig. 5. The LSB error is caused in about 7 μs after the sampling of 2 μs. The clock signal was controlled by 400 ns per 1 bit, and the 16 bit conversion is completed during with 6.4 μs. Thus, a stable output was obtained by the voltage follower of the output stage.

Figure 5.

Entire circuit diagram of designed SAR ADC.

Figure 6.

Simulation results of (a) sample and hold, (b) R-2R ladder DAC comparator.

Figure 7.

The calculated average power consumption and current simulation of designed SAR DAC.

Figure 8.

Overall layout of designed SAR ADC.

In the SAR ADC, the comparator is a circuit that plays an important role in the ADC as a quantizer of 1 bit, and it produces a digital signal that compared with the output of the sample and hold and the DAC. The structure of the comparator consists of an amplifier, latch and buffer. In order to minimize the offset voltage and power consumption of the designed comparator, we designed a preamplifier with current mirror. Therefore, the power consumption was reduced by the power control switch used in the comparator. A stable output was obtained by the buffer.

2.3Simulation of designed SAR ADC

In this paper, we designed an SAR ADC for fully implantable hearing aids. The circuit simulation was performed using the Spectre circuit simulator (Cadence, USA). The simulation result of the designed SAR ADC is shown in Fig. 6. As a simulation result, the analog input signal was sampled and was held by a control signal. Thus, the R-2R DAC output has been approximated to the held signal input and we confirmed that the corresponding digital code was output. The current simulation was performed using a circuit simulator Spectre (Cadence, USA), as shown in Fig. 7. The average power consumption was calculated by Eq. (1), which was provided in the simulation software, where P𝑎𝑣𝑔 is the average power, P⁢(t) is the instantaneous power, and T is the time period. As a simulation result, the power consumption of 50 μW was confirmed.