Affiliations: Electronics Platform Development Team, Hyundai Motor
Company, Republic of Korea | School of Electrical and Electronic Engineering,
Yonsei University, Seoul, Republic of Korea
Note: [] Corresponding author: Won W. Ro, School of Electrical and
Electronic Engineering, Yonsei University, 262 Seongsanno, Seodaemun-gu Seoul
120-749, Seoul, Republic of Korea. Tel.: +82 2 2123 5769; Fax: +82 2 313 287;
E-mail: [email protected]
Abstract: Network coding is a promising technique for data communications in
wired and wireless networks. However, it places an additional computing
overhead on the receiving node in exchange for the improved bandwidth. This
paper proposes an FPGA-based reconfigurable and parallelized network coding
decoder for embedded systems especially for vehicular ad hoc networks. In our
design, rapid decoding process can be achieved by exploiting parallelism in the
coefficient vector operations. The proposed decoder is implemented by using a
modern Xilinx Virtex-5 device and its performance is evaluated considering the
performance of the software decoding on various embedded processors. The
performance on four different sizes of the coefficient matrix is measured and
the decoding throughput of 18.3 Mbps for the size 16 ×
16 and 6.5 Mbps for 128 × 128 has been achieved at the
operating frequency of 64.5 MHz. Compared to the recent TEGRA 250 processor,
the result obtained with128 × 128 coefficient matrix
reaches up to 5.06 in terms of speedup.
