High-Performance Digital Defuzzification and Defuzzifier Circuit

Article type: Research Article

Authors: Patyra, Marek J. | Braun, Eric | VanMeeteren, Mike

Affiliations: Department of Electrical and Computer Engineering, University of Minnesota, Duluth, MN 55812-2496

Abstract: This article discusses the design and development of a high-speed digital defuzzifier circuit that can be used as a stand alone chip associated with a conventional or fuzzy logic processor or as a macrofunctional block built into the fuzzy logic processor chip. As a case example, the presented defuzzifier circuit is designed to have 64*5 bit input data bus and 32 bit output data bus. The choice of the input/output data bus size is arbitrary and the design can be modified according to the user's needs. The output data bus, representing the scalar output value, is organized in such a way that the first 8 bits represent the real number and the remaining 24 bits represent its fraction. The accuracy of the defuzzification equals 11256. The defuzzifier is pipelined to assist in higher throughput, and therefore, for a used technology (n-well 1.2-μm CMOS) its maximum frequency of operation is 100 MHz. This means that as soon as the pipeline is filled, the defuzzifier reads 64*5 bit fuzzy input and generates the 32-bit scalar output every 10 ns. This defuzzifier, as an element of the fuzzy logic controller design, was simulated at the postlayout stage of development.

DOI: 10.3233/IFS-1996-4207

Journal: Journal of Intelligent and Fuzzy Systems, vol. 4, no. 2, pp. 161-173, 1996