Affiliations: [a] Department of Electrical and Electronics Engineering, Bannari Amman Institute of Technology, Sathyamangalam, Tamil Nadu, India
| [b] Department of Electronics and Communication Engineering, Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Chennai, Tamil Nadu, India
| [c] Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam, Tamil Nadu, India
Correspondence:
[*]
Corresponding author. P. Sritha, Bannari Amman Institute of Technology, Erode, Tamilnadu, India. E-mail: [email protected].
Abstract: One of the best methods for assessing a baby’s health is foetal electrocardiography (FECG). Previously restricted to more widespread global disorders such as common ischemia, it is new way to investigating foetal heart rate irregularities. Current prenatal monitoring practices ignore critical FECG waveform elements that are the foundation of both pediatric, adult cardiac assessment, and instead of focusing solely on the foetal heart rate. In this paper we proposed Double Multiply-and-Accumulate (MAC) approach used for package operators into a single DSP block of commercial FPGAs, theoretically doubling the calculation speed for FECG monitoring. For a variety of technical reasons, they were using the Space-Time Block Code (STBC) monitoring mode of operation. To strengthen the security of FECG monitoring, the Advanced Encryption Standard (AES) method may be used with the double MAC operators using STBC based FECG monitoring that has been developed. The solution was then assessed using state-of-the-art the Space-Time Block Code (STBC) based FECG techniques, and its validity was confirmed using Verilog simulation and FPGA synthesis. The calculation throughput of an STBC-based FECG monitoring system was found to be doubled using the Double MAC approach. Our implementation result demonstrates that keys are necessary for 128-bit AES encoding and decoding operations via VHDL-coded transformations. It is now more vital than ever to do a feasibility analysis of any hardware design due to the increase in the number of ways presented for minimizing noise. The efficiency increased (92%), and the delay was decreased to 19.35 ns by employing this double MAC architecture. The simulation results demonstrate that transformations for coding on an FPGA are implemented using the Xilinx VIVADO tool.
