Affiliations: [a]
Department of ECE, Sri Krishna College of Technology, Coimbatore, Tamil Nadu, India
| [b]
Department of ECE, Dr.N.G.P. Institute of Technology, Coimbatore, Tamil Nadu, India
| [c]
Department of ECE, Muthayammal College of Engineering, Rasipuram, Namakkal, Tamil Nadu, India
| [d] Vice Principal, Department of ECE, KGiSL Institute of Technology, Coimbatore, Tamil Nadu, India
Correspondence:
[*]
Corresponding author. M. Thillai Rani, Department of ECE, Sri Krishna College of Technology, Coimbatore, Tamil Nadu, India. E-mail: [email protected].
Abstract: Electronics industry has attained huge development in last few decades due to the rapid increase in system design applications. With the growth of very large scale integration (VLSI) design, integrated circuits (ICs) are employed in many applications. VLSI design comprises many steps like system-level design, high-level synthesis (HLS), logic design, test generation, and physical design. HLS interprets behavior description and create digital hardware that executes the behavior. But, the power-process-voltage-temperature (PPVT) variation can causee many issues and reduce the performance of VLSI design circuits. In order to address these problems, Recurrent Deep Neural Learning Classification based High Level Synthesis (RDNLC-HLS) Model is designed for better runtime adaptability with minimal time consumption. VLSI circuits are designed with the behavioral input and the output performance is measured at runtime. The behavioral description of the circuit is taken as input. Then, source code compilation process translates high level specification into Intermediate Representation (IR) and converts to control/data flow graph (CDFG). CDFG reveals data and control dependencies between operations. The proposed Recurrent Deep Neural Learning Classification based High Level Synthesis (RDNLC-HLS) Model is designed for providing better runtime adaptability with minimal time consumption. Finally, Register Transfer Level Generation is carried out to yield better runtime adaptability with minimal time. Simulation results on ISCAS’89 Benchmark Dataset, shows that the RDNLC-HLS model increases the FUSA with minimal error rate and CAT.
Keywords: Deep learning, neural network, optimization techniques, VLSI circuits
