Affiliations: Department of Electronics and Communication Engineering, PET Engineering College, Vallioor, Tirunelveli District, Tamilnadu, India | Department of Electronics and Communication Engineering, Mepco Schlenk Engineering College, Sivakasi, Tamil Nadu, India
Note: [] Corresponding author. P. Kannan, Professor, Department of Electronics and Communication Engineering, PET Engineering College, Vallioor-627117, Tirunelveli District, Tamilnadu, India. E-mail: [email protected]
Abstract: VLSI architecture for face recognition system based on Local Gabor XOR Pattern (LGXP) feature extraction method is presented in this paper. LGXP is utilized to encode Gabor phase variations and to extract feature with the help of Gabor filter and Local XOR Pattern (LXP) operator. VLSI architecture for Gabor Filter and a Behavioral model for LXP operator for feature extraction are investigated. Also a behavioral model for Similarity matching is designed using Verilog language. The similarity matching for face recognition is executed by L1 distance measure. Therefore our approach explores the effectiveness of Gabor phase information on FPGA platform by addressing the drawbacks like computational complexity and hardware complexity by mapping the algorithms. The proposed approach is designed on virtex-5 device using Veriolg HDL in Xilinx ISE tool and the logic utilization results will be generated using synthesis tool while the power consumption report will be analyzed using Xpower analysis tool. Also the effectiveness of our design is evaluated with FAR, FRR and accuracy plot in Matlab simulation environment. Research outcome of our proposed face recognition system over UPC face database is 72.225% Accuracy for distance matching threshold of ‘5’.
