Adapting Pfair scheduling for symmetric multiprocessors

Issue title: Cache exploitation in embedded systems

Article type: Research Article

Authors: Holman, Philip | Anderson, James H.

Affiliations: Department of Computer Science, University of North Carolina, USA

Note: [] Corresponding author. E-mail: [email protected]

Abstract: We consider the implementation of a Pfair real-time scheduler on a symmetric multiprocessor (SMP). Although SMPs are in many ways well-suited for Pfair scheduling, experimental results presented herein suggest that bus contention resulting from the simultaneous scheduling of all processors can substantially degrade performance. To correct this problem, we propose a staggered model for Pfair scheduling that strives to improve performance by more evenly distributing bus traffic over time. Additional simulations and experiments with a scheduler prototype are presented to demonstrate the effectiveness of the staggering approach. In addition, we discuss other techniques for improving performance while maintaining worst-case predictability. Finally, we present an efficient scheduling algorithm to support the proposed model and briefly explain how existing Pfair results apply to staggered scheduling.

Keywords: SMP, Pfairness, real-time, scheduling, bus, multiprocessor

Journal: Journal of Embedded Computing, vol. 1, no. 4, pp. 543-564, 2005