Abstract: This paper proposes an efficient cache scheme to reduce power
consumption and conflict misses for single-core or multi-core embedded
computing architecture. The proposed cache requires an additional gate stage
before it accesses the cache line, which allows the use of a buffer to save the
last memory reference. Each memory reference can be checked in the buffer
before accessing the cache. If the data is in the buffer, the cache access can
be aborted to reduce power consumption. Our simulation results show that it can
reduce power consumption, access penalty, and cache misses significantly
compared to other conventional caches such as direct-mapped and 2-way
set-associative.