Affiliations: [a] Department of Artificial Intelligence and Data Science, Velalar College of Engineering and Technology, Erode, India | [b] Department of Electronics and Communication Engineering, Karpagam Institute of Technology, Coimbatore, India | [c] Department of Computer Science and Engineering, Nandha Engineering College, Erode, India | [d] Department of Computer Science and Engineering, SRM Institute of Science & Technology, Vadapalani, Chennai, India
Correspondence:
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Corresponding author: Sadesh S, Department of Artificial Intelligence and Data Science, Velalar College of Engineering and Technology, Erode, India. E-mail: [email protected].
Abstract: The promising Network-on-Chip (NoC) model replaces the existing system-on-chip (SoC) model for complex VLSI circuits. Testing the embedded cores using NoC incurs additional costs in these SoC models. NoC models consist of network interface controllers, Internet Protocol (IP) data centers, routers, and network connections. Technological advancements enable the production of more complex chips, but longer testing times pose a potential problem. NoC packet switching networks provide high-performance interconnection, a significant benefit for IP cores. A multi-objective approach is created by integrating the benefits of the Whale Optimization Algorithm (WOA) and Grey Wolf Optimization (GWO). In order to minimize the duration of testing, the approach implements optimization algorithms that are predicated on the behavior of grey wolves and whales. The P22810 and D695 benchmark circuits are under consideration. We compare the test time with existing optimization techniques. We assess the effectiveness of the suggested hybrid WOA-GWO algorithm using fourteen established benchmark functions and an NP-hard problem. This proposed method minimizes the time needed to test the P22810 benchmark circuit by 69%, 46%, 60%, 19%, and 21% compared to the Modified Ant Colony Optimization, Modified Artificial Bee Colony, WOA, and GWO algorithms. In the same vein, the proposed method reduces the testing time for the d695 benchmark circuit by 72%, 49%, 63%, 21%, and 25% in comparison to the same algorithms. We experimented to determine the time savings achieved by adhering to the suggested procedure throughout the testing process.
Keywords: Test time, whale optimization algorithm, test access mechanism, grey wolf optimization, test scheduling, network-on-chip
