Hazard-free self-timed design: methodology and application

Article type: Research Article

Authors: Senn, Eric^{a; *} | Perona, P.^b

Affiliations: [a] DGA, Centre Technique d'Arcueil, Département GIP, 94114 Arcueil Cedex, France | [b] Institut d'Electronique Fondamentale, Université Paris XI, 91405 Orsay Cedex, France

Correspondence: [*] Corresponding author.

Abstract: This paper introduces an original methodology for hazard-free self-timed design, assuming the worst conditions for robustness. Hazards are classified under three types. Equation hazards are eliminated by an optimal covering. A new variable, labeled state-trajectory is proposed: its integrity guarantees immunity to function hazards. The choice of the delay model for implementation guarantees immunity to logic hazards. Signal-transition graph constraints support safe interaction with synchronous processes. The method was applied to the VLSI CMOS implementation of a router for a parallel machine. Specific cells are designed. Measured performances are presented.

DOI: 10.3233/ICA-2000-7304

Journal: Integrated Computer-Aided Engineering, vol. 7, no. 3, pp. 229-242, 2000