Affiliations: [a] Department of Intelligent Systems, Graduate School of Information Science and Electrical Engineering, Kyushu University, 6-1, Kasuga-koen, Kasuga, Fukuoka 816, Japan. E-mail: [email protected], [email protected] | [b] KFKI Research Institute for Measurement and Computing Techniques, H-1525 Budapest, P.O.Box 49, Hungary. E-mail: [email protected], [email protected]
Abstract: There are two fundamental problems to be solved in any scalable computer system: tolerate and hide latency of remote accesses, and, tolerate and hide idling due to synchronization among parallel processes. Architectures which can not solve these issues will fail in building large-scale parallel processing systems. One possible solution for tolerating memory and synchronization latency is the introduction of threads and fast context switching mechanism among threads. Systems which support this technique are called multithreaded systems. Multimedia applications usually require large computing power and thus, massivelly parallel systems are good candidates for such tasks. Additionally, multimedia applications usually involve the processing of huge amount of data (e.g. audio or video information), therefore both the classical shared or distributed memory parallel systems may be inadequate for fulfilling all the needs. Finally, multimedia applications (e.g. image processing) in some cases may require other computing model than current commodity RISC processors can provide. A range of multithreaded architectures can be idealistic for multimedia applications, which is massively parallel, has distributed memory for the sake of scalability. Such architectures, which support remote memory accesses, may be a proper combination of different computing models, e.g. von Neumannn and dataflow ones. In this paper, the design space of multithreaded architectures is introduced, and a certain architecture, called KUMP/D (Kyushu University Multimedia Processor on Datarol-II) is described. It is also shown how a multithreaded architecture can be built in a short design cycle by using a commercial high-end microprocessor and easily programmable hardware devices.
