A Technique for Estimating Signal Activity in Logic Circuits

Article type: Research Article

Authors: Xie, Hong-Yu^a | Vrudhula, Sarma B.K.^{b; *}

Affiliations: [a] Unified Design System Laboratory, Motorola Inc., MD EL714, 2100 E. Elliot Rd., Tempe AZ 85284, USA | [b] Center for Low Power Electronics, ECE Department, University of Arizona, Tucson, AZ 85721, USA

Correspondence: [*] Correspondence to: Dr. S.B.K. Vrudhula.

Abstract: In this paper an efficient technique for estimating the average number of signal transitions in CMOS logic circuits is presented. A logic signal is modeled as a two state, discrete-time Markov chain, that is characterized by two parameters. The steady-state average number of transitions on a signal is expressed as a function of the Markov chain parameters. Formulas for the two parameters associated with the gate output as a function of the corresponding parameters associated with the gate input are derived. This allows estimation of signal transitions at all gates by local propagation of the parameters. For circuits without reconvergent, the local propagation provides very accurate estimates and the time to obtain the estimates is a negligible fraction of the time required to perform logic simulation. For circuits with reconvergent fanout, the estimation procedure is based on the (local) use of OBBDs. This scheme has the exibility of trading off between speed and accuracy by allowing the user to specify the number of levels of reconvergent fanout that are to considered. Results of experiments carried out on a large number of benchmark circuits are given. The theoretical estimates of switching activity are compared with those obtained via simulation. The experiments also examine the number of levels of logic that need to be examined in the presence of reconvergent fanout.

DOI: 10.3233/ICA-1998-5205

Journal: Integrated Computer-Aided Engineering, vol. 5, no. 2, pp. 141-152, 1998