Analytical Model for the CMOS Short-Circuit Power Dissipation

Article type: Research Article

Authors: Bisdounis, L.^{a; *} | Nikolaidis, S.^b | Koufopavlou, O.^a

Affiliations: [a] VLSI Design Laboratory, Department of Electrical & Computer Engineering, University of Patras, 26500 Patras, Greece | [b] Electronics & Computers Division, Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki, Greece

Correspondence: [*] Correspondence to: Dr. L. Bisdounis

Abstract: A significant part of the power dissipation in CMOS digital circuits is due to the short-circuit currents. In this paper an accurate analytical model for the evaluation of the CMOS short-circuit power dissipation, on the basis of a CMOS inverter, is presented. The innovation of the proposed approach against previous works is due to the accurate, analytical expressions of the inverter output waveform which include for the first time the effects of both transistor currents and the gate-to-drain coupling capacitance. The α-power law MOS model which considers the carriers' velocity saturation effects of short-channel devices is used. The results produced by the suggested model show very good agreement with SPICE simulations.

DOI: 10.3233/ICA-1998-5204

Journal: Integrated Computer-Aided Engineering, vol. 5, no. 2, pp. 129-140, 1998