Power Estimation Under Uncertain Delays*

Article type: Research Article

Authors: Chou, Tan-Li | Roy, Kaushik^{; **}

Affiliations: Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA

Correspondence: [**] To whom correspondence should be addressed.

Note: [*] This work was financially supported by “Comite para el Desarrollo de la Investigation-CODI-UdeA (grant to CVP)”.

Abstract: While estimating glitches or spurious transitions is a challenge due to signal correlations, the random behavior of logic gate delays makes the estimation problem even more difficult. In this paper, we present statistical estimation of signal activity at the internal and output nodes of combinational Complementary Metal-Oxide-Semiconductor (CMOS) logic circuits considering uncertainty of gate delays. The methodology is based on the stochastic models of logic signals and the probabilistic behavior of gate delays due to process variations, interconnect parasitics, etc. We propose a statistical technique of estimating average-case activity, which is exible in adopting different delay models and variations and can be integrated with worst-case analysis into statistical logic design process. Experimental results show that the uncertainty of gate delays has a great impact on activity at individual nodes (more than 100%) and total power dissipation (can be overestimated up to 65%) as well.

DOI: 10.3233/ICA-1998-5202

Journal: Integrated Computer-Aided Engineering, vol. 5, no. 2, pp. 107-116, 1998