Low Power VLSI Design Techniques - The Current State

Article type: Review Article

Authors: Carothers, Jo Dale^{; *} | Radjassamy, Radjakichenin

Affiliations: Department of Electrical and Computer Engineering, The University of Arizona, Tucson, AZ 85721, USA

Correspondence: [*] Correspondence to: Prof. J.D. Carothers.

Abstract: Increasing demand for portable electronics for computing and communication, as well as other applications, has necessitated longer battery life, lower weight, and lower power consumption. In order to satisfy these requirements, research activities focusing on low power/low voltage design techniques are underway. Since 'power' is now one of the design decision variables, the expanded design space required for low power has further increased the complexity of an already non-trivial task. Low power design basically involves two concomitant tasks: power estimation and analysis and power minimization. These tasks need to be carried out at each of the levels in the design hierarchy, namely, the behavioral, architectural, logic, circuit and physical levels. In this survey of the current state of the field, many of the salient power estimation and minimization techniques proposed for low power VLSI design are reviewed. For each of the design levels, we provide an overview of several power estimation and minimization approaches and the CAD tools that support them. Finally, future research issues are discussed that will be necessary in order to make the low power design endeavor a successful one.

DOI: 10.3233/ICA-1998-5206

Journal: Integrated Computer-Aided Engineering, vol. 5, no. 2, pp. 153-176, 1998