Journal of Embedded Computing - Volume 2, issue 1

Authors: Bartolini, S. | Foglia, P. | Prete, C.A.

Article Type: Other

Citation: Journal of Embedded Computing, vol. 2, no. 1, pp. 1-3, 2006

Authors: Yehia, Sami | Collard, Jean-Francois | Temam, Olivier

Article Type: Research Article

Abstract: Indirect memory accesses, where a load is fed by another load, are ubiquitous because of rich data structures and sophisticated software conventions, such as the use of linkage tables and position independent code. Unfortunately, they can be costly: if both loads miss, two round trips to memory are required even though the role of the first load is often limited to fetching the address of the second load. To reduce the total latency of such indirect …accesses, a new instruction called load squared is introduced. A load squared does two fetches, the first fetch reading the target address of the second. (An offset is optionally added to the result of the first fetch.) The load squared operation is performed by memory-side logic (typically, the memory controller if it isn't located on the main processor chip). In this study, load squared is not an architecturally visible instruction: the micro-architecture transparently decides which loads should be replaced by loads squared. We show that performance is sometimes improved significantly, and never degraded. Show more

Citation: Journal of Embedded Computing, vol. 2, no. 1, pp. 5-14, 2006

Authors: Surendra, G. | Banerjee, Subhasis | Nandy, S.K.

Article Type: Research Article

Abstract: The effectiveness of Instruction Reuse (IR) – a technique to eliminate redundant computations at run time – is limited by the fact that performance gain seldom exceeds 3% and is dependent on the criticality of instructions being "reused". In this paper, we focus on the power aspect of IR and propose a "resultbus optimization" that exploits communication reuse to reduce the power dissipated over a high capacitance resultbus. The effectiveness of this optimization depends on the …number of result producing instructions that are reused and improves overall power and Energy-Delay Product (EDP) by 3% over a base IR policy for a 1024 entry "Reuse Buffer" (RB). As a domain specific study, we examine the impact of multithreading on IR in the context of packet header processing applications. Specifically, sharing the RB among threads can lead to either constructive or destructive interference, thereby increasing or decreasing the amount of IR that can be uncovered. Further, packet header processing applications are unique in the sense that repetition in data values within "flows" are quite prevalent which can be exploited to improve IR. We find that an architecture that uses this "flow" information to govern accesses to the RB improves IR by as much as 4.6% for header processing kernels. Show more

Keywords: Instruction reuse, computation reuse, value locality, flow aggregation, low power, resultbus power

Citation: Journal of Embedded Computing, vol. 2, no. 1, pp. 15-34, 2006

Authors: Zhang, Wei

Article Type: Research Article

Abstract: With the scaling of technology, leakage energy reduction has become increasingly important, especially for cache memories. Recent studies in drowsy instruction cache show that the leakage energy of the instruction cache can be significantly reduced with little performance degradation by exploiting the instruction spatial locality at the cache sub-bank level [5]. To hide the performance penalty due to the sub-bank wake-up latency, a prediction buffer is used to predict and pre-activate the next sub-bank at runtime. …However, consulting the prediction buffer at every cache access consumes non-trivial dynamical energy, which can compromise the overall energy savings substantially. This paper presents a more energy-efficient compiler-guided approach to capture the sub-bank transition behavior at link time and to pre-activate the instruction cache sub-bank at runtime based on the compiler-directed hints. We also propose a hybrid approach to exploit both the static and dynamic information for reducing the performance penalty further with little dynamic energy overhead. Our experiments reveal that the static approach is very successful in capturing the sub-bank transition behavior to reduce the performance penalty and it also reduces 38.2% more leakage energy than the hardware-based approach, taking the dynamic energy overhead into account. Moreover, our results show that the hybrid approach is the best strategy for the drowsy instruction cache to balance leakage energy reduction and performance. Show more

Keywords: Drowsy instruction cache, leakage energy, compiler, sub-bank prediction, prediction buffer

Citation: Journal of Embedded Computing, vol. 2, no. 1, pp. 35-48, 2006

Authors: Fujii, Seiichiri | Sakanaka, Akihito | Chiyonobu, Akihiro | Sato, Toshinori

Article Type: Research Article

Abstract: Power consumption is becoming one of the most important constraints for microprocessor design in nanometer-scale technologies. Especially, as the transistor supply voltage and threshold voltage are scaled down, leakage energy consumption is increased even when the transistor is not switching. This paper proposes a simple technique to reduce the static energy due to subthreshold leakage current. The key idea of our approach is to allow the ways within a cache to be accessed at different speeds …and to place infrequently accessed data into the slow ways. We use dual-V_{t} technique to realize the non-uniform set-associative cache, and propose a simple replacement policy to reduce average access latency. Experimental results on 32-way set-associative caches demonstrate that any severe increase in clock cycles to execute application programs is not observed and significant static energy reduction can be achieved, resulting in the improvement of energy-delay^{2} product. Show more

Keywords: Leakage current, cache memories, embedded processors

Citation: Journal of Embedded Computing, vol. 2, no. 1, pp. 49-55, 2006

Authors: Milenkovic, Aleksandar | Milenkovic, Milena | Jovanov, Emil

Article Type: Research Article

Abstract: Embedded system designers face a unique set of challenges in making their systems more secure, as these systems often have stringent resource constraints or must operate in harsh or physically insecure environments. One of the security issues that have recently drawn attention is software integrity, which ensures that the programs in the system have not been changed either by an accident or an attack. In this paper we propose an efficient hardware mechanism for runtime verification …of software integrity using encrypted instruction block signatures. We introduce several variations of the basic mechanism, and give details of three techniques that are most suitable for embedded systems. Performance evaluation using selected MiBench, Mediabench, and Basicrypt benchmarks indicates that the considered techniques impose a relatively small performance overhead. The best overall technique has performance overhead in the range 0–8%, when protecting 128-byte instruction blocks with 16-byte signatures. With 64-byte instruction blocks, the overhead is in the range 0–15%; the average overhead with 8~KB cache is 1%. With additional investment in a signature cache, this overhead can be almost completely eliminated. Show more

Keywords: Computer architecture, embedded systems, secure computing, processor design, performance evaluation, security attacks, decryption

Citation: Journal of Embedded Computing, vol. 2, no. 1, pp. 57-76, 2006

Authors: Verdú, Javier | García, Jorge | Nemirovsky, Mario | Valero, Mateo

Article Type: Research Article

Abstract: The trend of the networking processing is to increase the intelligence of the routers (i.e. security capacities). This means that there is an increment in the workload generated per packet and new types of applications are emerging, such as stateful programs. On the other hand, Internet traffic continues to grow vigorously. This fact involves an increment of the traffic aggregation levels and overloades the processing capacities of the routers. In this paper we show …the importance of traffic aggregation level on networking application studies. We also classify the applications according to the data management of the packet processing. Hence, we present the different impacts on the data cache performance depending on the application category. Our results show that traffic aggregation level may affect the cache performance depending on the networking application category. Stateful applications show a significant sensitivity to this impact. Show more

Keywords: Traffic, aggregation, stateless, stateful, flows

Citation: Journal of Embedded Computing, vol. 2, no. 1, pp. 77-82, 2006

Authors: Arakawa, F. | Ishikawa, M. | Kondo, Y. | Kamei, T. | Nishii, O. | Hattori, T.

Article Type: Research Article

Abstract: A SuperH™ embedded processor core SH-X implemented in a 130-nm CMOS process running at 400~MHz achieved 720 MIPS and 2.8 GFLOPS at a power of 250 mW under worst-case conditions. It has a dual-issue seven-stage pipeline architecture, but reaches the 1.8 MIPS/MHz of the previous five-stage processor. The on-chip memory configuration is tuned for digital consumer appliances. A new resume-standby mode enables a standby current of less than 100 μA and a 3-ms recovery time. The …processor meets the requirements of a wide range of applications, and is suitable for digital appliances aimed at the consumer market, such as cellular phones, digital still/video cameras, and car navigation systems. Show more

Citation: Journal of Embedded Computing, vol. 2, no. 1, pp. 83-90, 2006

Authors: Saket, Rishi | Navet, Nicolas

Article Type: Research Article

Abstract: The set of frames exchanged in automotive applications must meet two constraints: it has to be feasible from a schedulability point of view and it should minimize the network bandwidth consumption. This latter point is important since it allows the use of low cost electronic components and it facilitates an incremental design process. The purpose of this study is to propose efficient algorithms for solving the NP-hard problem of generating a set of schedulable frames that …minimize the bandwidth usage. This study presents novel algorithms for building bandwidth-minimizing sets of frames that meet the schedulability requirement. In our experiments, these proposals have proved to be more effective than the existing approaches. Show more

Keywords: Embedded systems, scheduling algorithms, controller area network, heuristics, bandwidth-minimization problems

Citation: Journal of Embedded Computing, vol. 2, no. 1, pp. 93-102, 2006

Authors: O'Neil, Timothy W. | Sha, Edwin H.-M.

Article Type: Research Article

Abstract: Many applications commonly found in digital signal processing and image processing applications can be represented by data-flow graphs (DFGs). In our previous work, we proposed a new technique, extended retiming, which can be combined with minimal unfolding to transform a DFG into one which is rate-optimal. The result, however, is a DFG with split nodes, a concise representation for pipelined schedules. This model and the extraction of the pipelined schedule it represents have heretofore not been …explored. In this paper, we develop new results regarding the construction of such graphs. We develop scheduling algorithms for such graphs, and then discuss a way to reduce the hardware requirements of such schedules. In the process, we state and prove a tight upper bound on the minimum number of processors required to execute the static schedule produced by our algorithms. We also construct an unfolding algorithm for split-node graphs and combine it with our scheduling methods to achieve rate-optimality in all cases. Finally, we demonstrate our methods on a specific example. Show more

Keywords: Parallel and distributed systems, compilers, optimization, modeling languages, programmable signal processors

Citation: Journal of Embedded Computing, vol. 2, no. 1, pp. 103-117, 2006

Authors: Wang, Gang | Gong, Wenrui | Kastner, Ryan

Article Type: Research Article

Abstract: Modern digital systems consist of a complex mix of computational resources, e.g. microprocessors, memory elements and reconfigurable logic. System partitioning – the division of application tasks onto the system resources – plays an important role for the optimization of the latency, area, power and other performance metrics. This paper presents a novel approach for this problem based on the Ant Colony Optimization, in which a collection of agents cooperate using distributed and local heuristic information to …effectively explore the search space. The proposed model can be flexibly extended to fit different design requirements. Experiments show that our algorithm provides robust results that are qualitatively close to the optimal with minor computational cost. Compared with the popularly used simulated annealing approach, the proposed algorithm gives better solutions with substantial reduction on execution time for large problem instances. Moreover, a hybrid approach that combines our algorithm and SA achieves even better results with great runtime reduction. Show more

Keywords: System partitioning, ant colony optimization, hardware/software codesign, evolutionary computing, CAD

Citation: Journal of Embedded Computing, vol. 2, no. 1, pp. 119-136, 2006