Abstract: This paper presents an overview of the architecture for a broadband, high‐speed packet switch processor used in the TRW Gen*Star system. The first application of the Gen*Star design is the Astrolink program. TRW is currently in production of the 4th generation of digital communications processors. Features and benefits of several key capabilities of the processor design for space applications are presented in this paper. The high‐speed packet switch processor uses standard asynchronous transfer mode (ATM) cell structure, which conveys all the Quality of Service (QoS) characteristics of ATM to the Gen*Star network. A non‐blocking crossbar switch with overspeed and input arbitration optimizes switch performance and alleviates output port contention. The downlink has output priority queues with programmable downlink scheduling and adaptive coding that provides maximum flexibility for traffic control and QoS. The resource control function is a distributed architecture using a two‐layer approach that maximizes performance vs. weight and power.