Affiliations: [a] Department of Electrical and Electronics Engineering, Velalar College of Engineering and Technology, Affiliated to Anna University, Chennai, India
| [b] Department of Electronics and Communication Engineering, Saveetha School of Engineering, Saveetha Institute of Medical and Technical Sciences, Chennai, India
| [c] Department of Electronics and Communication Engineering, Anna University, Chennai, India
Correspondence:
[*]
Corresponding author. Gokul Chandrasekaran, Department of Electrical and Electronics Engineering, Velalar College of Engineering and Technology, Erode - 638012, Tamil Nadu, India. E-mail: [email protected].
Abstract: Test scheduling of System-on-Chip (SoC) is a major problem solved by various optimization techniques to minimize the cost and testing time. In this paper, we propose the application of Dragonfly and Ant Lion Optimization algorithms to minimize the test cost and test time of SoC. The swarm behavior of dragonfly and hunting behavior of Ant Lion optimization methods are used to optimize the scheduling time in the benchmark circuits. The proposed algorithms are tested on p22810 and d695 ITC’02 SoC benchmark circuits. The results of the proposed algorithms are compared with other algorithms like Ant Colony Optimization, Modified Ant Colony Optimization, Artificial Bee Colony, Modified Artificial Bee Colony, Firefly, Modified Firefly, and BAT algorithms to highlight the benefits of test time minimization. It is observed that the test time obtained for Dragonfly and Ant Lion optimization algorithms is 0.013188 Sec for D695, 0.013515 Sec for P22810, and 0.013432 Sec for D695, 0.013711 Sec for P22810 respectively with TAM Width of 64, which is less as compared to the other well-known optimization algorithms.
Keywords: System-on-chip, test scheduling, Dragonfly algorithm, Ant Lion optimization
