RTL power modeling and estimation of sleep transistor based power gating

Issue title: PATMOS 2007 selected papers on low power electronics

Article type: Research Article

Authors: Rosinger, Sven | Helms, Domenik | Nebel, Wolfgang

Affiliations: OFFIS Research Institute, D-26121 Oldenburg, Germany | University of Oldenburg, D-26121 Oldenburg, Germany

Note: [] Corresponding author. E-mail: [email protected]

Abstract: We present an accurate RT level estimation methodology describing the power consumption of a component under power gating. By developing separate models for the on- and off-state and the transition cost between them, we can limit errors to below 10% compared to SPICE. The models support several implementation styles of power gating as NMOS/PMOS or Super-Cutoff. Additionally the models can be used to size the sleep transistors more accurate. We show, how the models can be integrated into a high level power estimation framework supporting design space exploration for several design for leakage methodologies.

Keywords: Power modeling, power gating, leakage, leakage optimization, synthesis

DOI: 10.3233/JEC-2009-0091

Journal: Journal of Embedded Computing, vol. 3, no. 3, pp. 189-196, 2009