Affiliations: City University of Hong, Kowloon, Hong Kong | Hong Kong Polytechnic University, Kowloon, Hong
Kong | Wright State University, Dayton, OH, USA | University of New Orleans, New Orleans, LA,
USA | University of Texas at Dallas, TX, USA
Abstract: Embedded systems have strict timing and code size requirements.
Retiming is one of the most important optimization techniques to improve the
execution time of loops by increasing the parallelism among successive loop
iterations. Traditionally, retiming has been applied at instruction level to
reduce cycle period for single loops. While multi-dimensional (MD) retiming can
explore the outer loop parallelism, it introduces large overheads in loop index
generation and code size due to loop transformation. In this paper, we propose
a novel approach, that combines iterational retiming with instructional
retiming to satisfy any given timing constraint by achieving full parallelism
for iterations in a partition with minimal code size. The experimental results
show that combining iterational retiming and instructional retiming, we can
achieve 37% code size reduction comparing to applying iteration retiming
alone.
