Instruction level energy modeling for pipelined processors

Issue title: Low-power Embedded Systems

Article type: Research Article

Authors: Nikolaidis, S. | Kavvadias, N. | Laopoulos, T. | Bisdounis, L. | Blionas, S.

Affiliations: Department of Physics, Aritstotle University of Thessaloniki, 54124 Thessaloniki, Greece | INTRACOM S.A., Peania, Greece

Note: [] Corresponding author. Tel.: +30 2310 998078; Fax: +30 2310 998018; E-mail: [email protected]

Abstract: A new method for creating instruction level energy models for pipelined processors is introduced. This method is based on measuring the instantaneous current drawn by the processor during the execution of the instructions. An appropriate instrumentation set up was established for this purpose. According to the proposed method the energy costs (base and inter-instruction costs) are modeled in relation to a reference instruction (e.g. NOP). These costs incorporate inter-cycle energy components, which cancel each other when they are summed to produce the energy consumption of a program resulting in estimates with high accuracy. This is confirmed by the results. Also the dependencies of the energy consumption on the instruction parameters (e.g. operands, addresses) are studied and modeled in an efficient way.

Keywords: Instruction-level energy modeling, energy characterization, instantaneous current measurement, microprocessor

Journal: Journal of Embedded Computing, vol. 1, no. 3, pp. 317-324, 2005