Exploiting multilevel parallelism using OpenMP on a massive multithreaded architecture

Issue title: Issues in embedded single-chip multicore architectures

Article type: Research Article

Authors: Ródenas, David | Martorell, Xavier | Ayguadé, Eduard | Labarta, Jesús | Almási, George | Caşcaval, Călin | Castaños, José | Moreira, José

Affiliations: Barcelona Supercomputing Center, UPC, Campus Nord – C6, Jordi Girona 1–3, 08034 Barcelona, Spain | IBM T.J. Watson Research Center, 1101 Kitchawan Road, Route 134, Yorktown Heights, NY 10598, USA

Note: [] Corresponding author. Tel.: +34 93 405 40 42; Fax: +34 93 401 70 55; E-mail: [email protected]

Abstract: This paper evaluates and analyzes multilevel parallelism on a chip multiprocessor (CMP) architecture. The environment is based on the experimental IBM BG/Cyclops architecture, where we have run the multi–zone parallel benchmarks. Multilevel parallelism is spawned using the Nanos OpenMP execution environment. We have performed the analysis with different execution parameters in order to evaluate different hardware threads distributions, cache utilization, and thread grouping configurations. Our results demonstrate that a large number of thread groups and good balancing algorithms are critical for high performance. We also show that a small number of threads can share the same data cache to increase the performance, but a large number of threads should better not share the same data caches.

Keywords: Multiprocessor on-a-chip, Multithreaded architectures, multilevel parallelism, OpenMP, runtime systems, multizone benchmarks, cache behaviour analysis

Journal: Journal of Embedded Computing, vol. 2, no. 2, pp. 141-155, 2006