Affiliations: [a] Department of Electronics Engineering KNlT Sultanpur Affiliated to Dr APJ Abdul Kalam Technology University Lucknow, U.P., India | [b] Anchor Semiconductor California, Santa Clara, USA | [c] Arrow Electronics, Gautam Buddh Nagar U.P., India | [d] DSMNRU (Government of India) University, Lucknow, U.P., India
Correspondence:
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Corresponding author: Gyan Prabhakar, Faculty of Electronics Engineering Technology, AKTU University, Lucknow, U.P, India. E-mail: [email protected].
Abstract: This paper proposes a new architecture using integrated inductor and MOS capacitor based on Dickson charge pump associated with two parallel LC circuit after the first stage and output stage which cancel the ripple voltage that is generated in the output stage. In this circuit, the MOS capacitor as used instead of pumping capacitor, which helps in reducing the circuit Silicon area. Efficiency up to 80–90% can be achieved by reducing the parasitic effects and by using a MOS capacitor. The efficiency conversion and voltage gain increase or decreases depending on inductor and capacitor values. Vt drop loss is managed using high voltage clock. It shows that 3.5 V output voltage is generated from input voltage of 1.0 V with five stages of MOS capacitor (used as Pumping capacitor) in working frequency of 100 MHz the simulations were performed in Cadence Virtuoso platform with 0.18 μm CMOS process.
