Evolution of application-specific cache mappings

Article type: Research Article

Authors: Ho, Nam^a | Kaufmann, Paul^{b; *} | Platzner, Marco^c

Affiliations: [a] Institute for Advanced Simulation, Jülich, Germany | [b] Mainz University, Germany | [c] Paderborn University, Germany

Correspondence: [*] Corresponding author: Paul Kaufmann, Mainz University, Germany. E-mail: [email protected].

Abstract: Reconfigurable caches offer an intriguing opportunity to tailor cache behavior to applications for better run-times and energy consumptions. While one may adapt structural cache parameters such as cache and block sizes, we adapt the memory-address-to-cache-index mapping function to the needs of an application. Using a LEON3 embedded multi-core processor with reconfigurable cache mappings, a metaheuristic search procedure, and MiBench applications, we show in this work how to accurately compare non-deterministic performances of applications and how to use this information to implement an optimization procedure that evolves application-specific cache mappings for the LEON3 multi-core processor.

Keywords: Evolvable hardware, caches, cartesian genetic programming

DOI: 10.3233/HIS-200281

Journal: International Journal of Hybrid Intelligent Systems, vol. 16, no. 3, pp. 149-161, 2020