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Article type: Research Article
Authors: Katoozian, Daniala | Hosseini-Nejad, Hosseina; * | Abolghasemi Dehaqani, Mohammad-Rezab; c; d | Shoeibi, Afshine | Manuel Gorriz, Juane; f
Affiliations: [a] FPGA Laboratory, Faculty of Electrical Engineering, K. N. Toosi University of Technology, Tehran, Iran | [b] Cognitive Systems Laboratory, Control and Intelligent Processing Center of Excellence, School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran | [c] School of Cognitive Sciences, Institute for Research in Fundamental Sciences, Tehran, Iran | [d] Pasargad Institute for Advanced Innovative Solutions (PIAIS), Tehran, Iran | [e] Data Science and Computational Intelligence Institute, University of Granada, Granada, Spain | [f] Department of Psychiatry, University of Cambridge, Cambridge, UK
Correspondence: [*] Corresponding author: Hossein Hosseini-Nejad, Faculty of Electrical Engineering, K. N. Toosi University of Technology, Seyed-Khandan, Shariati Ave., Tehran, Iran. E-mail: [email protected].
Abstract: Motor intention decoding is one of the most challenging issues in brain machine interface (BMI). Despite several important studies on accurate algorithms, the decoding stage is still processed on a computer, which makes the solution impractical for implantable applications due to its size and power consumption. This study aimed to provide an appropriate real-time decoding approach for implantable BMIs by proposing an agile decoding algorithm with a new input model and implementing efficient hardware. This method, unlike common ones employed firing rate as input, used a new input space based on spike train temporal information. The proposed approach was evaluated based on a real dataset recorded from frontal eye field (FEF) of two male rhesus monkeys with eight possible angles as the output space and presented a decoding accuracy of 62%. Furthermore, a hardware architecture was designed as an application-specific integrated circuit (ASIC) chip for real-time neural decoding based on the proposed algorithm. The designed chip was implemented in the standard complementary metal-oxide-semiconductor (CMOS) 180 nm technology, occupied an area of 4.15 mm2, and consumed 28.58 μW @1.8 V power supply.
Keywords: Implantable brain machine interface, real-time intra-cortical neural signal decoding, spike train temporal information, hardware implementation
DOI: 10.3233/ICA-220687
Journal: Integrated Computer-Aided Engineering, vol. 29, no. 4, pp. 431-445, 2022
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