Implementing fine grain processor arrays on field-programmable logic

Article type: Research Article

Authors: Vassányi, I.

Affiliations: Department of Information Systems, University of Veszprém, H-8200 Veszprém, Hungary. E-mail: [email protected]

Abstract: The structure of Field Programmable Gate Arrays (FPGAs) naturally fits that of fine grain array algorithms. The paper investigates the geometrical and layout-related implementation problems of FPGA-based processor arrays. A general methodology for implementing parametrized array processors on FPGAs is presented. Then, a detailed layout algorithm is proposed. A new feature of the algorithm is the uniform treatment of inter- and intra-module nets that allows the layout of the basic processor to be optimized with respect to the critical path of the whole, arbitrarily large processor array. The approach is demonstrated on a massively parallel processor array for binary morphology.

DOI: 10.3233/ICA-2000-7104

Journal: Integrated Computer-Aided Engineering, vol. 7, no. 1, pp. 53-66, 2000