A dedicated DSP architecture for discrete wavelet transform

Article type: Research Article

Authors: Desneux, P.^a | J.D. Legat, J.D.^{b; *}

Affiliations: [a] Alcatel Microelectronics, Excelsiorlaan, 44-46, B-1930 Zaventem, Belgium. E-mail: [email protected] | [b] Université Catholique de Louvain, Microelectronics Laboratory, Place du Levant, 3, B-1348 Louvain-la-Neuve, Belgium. E-mail: [email protected]

Correspondence: [*] Corresponding author.

Abstract: This paper presents the architecture of a DSP dedicated to discrete wavelet transform. The architecture consists in 2 microprogrammable processors whose complementarity enables to avoid any wait cycles during the algorithm execution so that the available computation power is continuously used. Thanks to this bi-processor organization, a 160000-transistor ASIC coupled to a small external SRAM implements in real time a 3-stage multiresolution transform on a CCIR 601 video signal. This chip has been realized in a 0.7 μm double metal CMOS technology. Moreover, the DSP has a full programmability with respect to the used filters and the picture format; it also has the possibility to take into account edge effects and therefore improve image quality. The circuit can be used in the coding as well as in the decoding.

DOI: 10.3233/ICA-2000-7204

Journal: Integrated Computer-Aided Engineering, vol. 7, no. 2, pp. 135-153, 2000