Affiliations: [a] ITALTEL, Central Research Labs, 20019 Castelletto di Settimo M.se MI, Italy | [b] Politecnico di Milano, Dip. Elettronica e Inform., P.zza L. Da Vinci 32, 20133 Milano, Italy E-mail: [email protected], [email protected]
Correspondence:
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Correspondence to: Dr. W. Fornaciari.
Abstract: The “pervasiveness” of silicon is going to enable the realization of all-on-a-chip systems for a wide range of embedded applications such as automotive, process control and telecom. The maturity of the digital synthesis CAD environments is shifting the designer's attention towards problems more related to a system-level trade-of analysis than in the past. However, common time-to-market constraints are forcing the CAD methodologies to provide quality/cost evaluation figures early in the design process, possibly in the valuable form of prediction. The goal is to dramatically reduce the number of complete synthesis cycles to achieve the optimal final product. The aim of this paper is to define some evaluation metrics to predict the characteristics of the final implementation, tailored for control-dominated hardware{software embedded systems, and to show their application in a complete example. The relevant features considered by the presented analysis cover the modularization of the system specification, the power consumption for both hardware and software, the silicon area of the hardware part and the memory size of the software components. The use of these estimation metrics within a co-design environment, called TOSCA, is also presented through an illustrative example.
