Case study of gate-level logic simulation on an extremely fine-grained chip multiprocessor

Issue title: Issues in embedded single-chip multicore architectures

Article type: Research Article

Authors: Gu, Pei | Vishkin, Uzi^;

Affiliations: Microsoft, USA | University of Maryland Institute for Advanced Computer Studies, College Park, MD, USA

Note: [] Corresponding author: 108 Swiss Stone CT. Cary, NC, 27513. Tel.: +1 919 4744991; E-mail: [email protected]

Abstract: Explicit-multi-threading (XMT) is a parallel programming approach for exploiting on-chip parallelism. Its fine-grained single program multiple data (SPMD) programming model is suitable for many computing intensive applications. In this paper, we present a parallel gate level logic simulator implemented on an XMT platform and study its performance. Test results show potential for achieving more than a hundred-fold speedup over a serial implementation. This indicates an interesting possibility for a certain type of a single chip multicore architecture: use an existing easy-to-program API, such as VHDL or Verilog, for reduced application-software development time and better performance over serial performance-driven languages, such as C.

Keywords: Fine-grained chip multiprocessors, explicit multi-threading, SPMD, parallel logic simulation, gate level logic simulation

Journal: Journal of Embedded Computing, vol. 2, no. 2, pp. 181-190, 2006