Abstract: Queue based instruction set architecture processor offers an
attractive option in the design of embedded systems by providing high
performance for a specific application. This work describes the design results
and methodology of a queue processor core, named QueueCore, as a starting point
for application-specific processor (ASP) design. By using simple and common
base queue instruction set, the design space exploration is focused on the
application-specific aspects of performance. In any new architecture, verification, which usually requires
complicated and lengthy software simulation of an emulated model, is an
important aspect. We show how cooperative hardware emulation, based on
programmable logic, can be integrated into a co-design flow to evaluate the
performance of the novel QueueCore processor and to verify the functional
correctness of a specific benchmark on the system core. To avoid duplication of the design effort, different target
implementations are derived from a common source. We present the evaluation
results of the QueueCore for three different platforms.
