Affiliations: University of California, Davis, USA | University of California, Santa Barbara, USA | California Polytechnic State University, San Luis
Obispo, USA
Note: [] Corresponding author: 2064 Kemper Hall, Davis, CA 95616-5294,
USA. Tel.: +1 530 752 1417
Abstract: We present an overview of the Synchroscalar single-chip, multi-core
processor. Through the design of Synchroscalar, we find that high energy
efficiency and low complexity can be attained through parallelization. The
importance of adequate inter-core interconnect is also demonstrated. We discuss
the impact of having multiple frequency and voltage domains on chip to reduce
the power consumption where parallelization fails. Finally, we investigate how
the ad-hoc selection of tile size that is currently used in most single-chip
multi-core processors impacts the power consumption of these architectures.
Keywords: Embedded processing, media processing, multicore processor, low-power
